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?002 fairchild semiconductor corporation 1 www.fairchildsemi.com november 2002 ace8001 product family arithmetic controller engine (acex) for low power applications ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex) for low power applications general description the ace8001 is a member of the acex (arithmetic controller engine) family of microcontrollers. it is a dedicated programma- ble monolithic integrated circuit for applications requiring high performance, low power, and small size. it is a fully static part fabricated using cmos technology. the ace8001 product family has an 8-bit core processor, 64 bytes of ram, 64 bytes of data eeprom and 1k bytes of code eeprom. its on-chip peripherals include a programmable 8-bit timer with pwm output, watch-dog/idle timer, and programma- ble undervoltage detection circuitry. the on-chip clock and reset functions reduce the number of required external components. the ace8001 product family is available in 8-pin soic and tssop packages. features arithmetic controller engine 1k bytes on-board code eeprom 64 bytes data eeprom fast startup (<10?) 64 bytes ram watchdog multi-input wake-up 3 i/o pins 8-bit timer1 with pwm output on-chip oscillator ?no external components ?1? instruction cycle time on-chip power-on reset ?external reset pin option (ACE8000) brown-out reset programmable read and write disable functions memory mapped i/o multilevel low voltage detection fully static cmos ?low power halt mode (100na @ 3.3v) ?power saving idle mode single supply operaton ?2.2 - 5.5v software selectable i/o options ?push-pull outputs with tri-state option ?weak pull-up or high impedance inputs 40 years data retention 1,000,000 writes 8-pin soic and tssop packages. block and connection diagram power-on reset brown-out reset ace1001 core (4 interrupt sources and vectors) programming interface 1k bytes of code eeprom 64 bytes of data eeprom 64 bytes of ram 12-bit timer0 with watchdog timer 8-bit pwm timer1 halt & idle power saving modes gport general purpose i/o with multi- input wakeup on 3 inputs internal oscillator vcc 1 gnd 1 reset (cko) g0 (cki) g1 (t1) g2 (miw) g4 (miw) g5 (miw) g3 2 1. 100nf decoupling capacitor recommended. 2. input only
2 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex) for low power applications figure 1: ace8001 soic 8-pin device pinout (a) normal operation (b) programming mode figure 2: ACE8000 soic 8-pin reset option (a) normal operation (b) programming mode figure 3: ace8001 tssop 8-pin device pinout (a) normal operation (b) programming mode (miw) g3 vcc gnd g2 (t1) g1 (cki) 1 2 3 45 6 7 8 (miw) g4 (cko) g0 (miw) g5 load vcc gnd sft_out cki 1 2 3 45 6 7 8 sft_in nc/vcc nc (miw) g3 vcc gnd g2 (t1) g1 (cki) 1 2 3 45 6 7 8 (miw) g4 (cko) g0 reset load vcc gnd sft_out cki 1 2 3 45 6 7 8 sft_in nc nc (miw) g3 vcc gnd g2 (t1) g1 (cki) 1 2 3 45 6 7 8 (miw) g4 g0 (cko) (miw) g5 load vcc gnd sft_out cki 1 2 3 45 6 7 8 sft_in nc nc/vcc
ace8001 product family arithmetic controller engine (acex) for low power applications 3 www.fairchildsemi.com ace8001 product family rev. b.2 2.0 electrical characteristics absolute maximum ratings ambient storage temperature -65 ? c to +150 ? c input voltage not including g3 -0.3v to v cc +0.3v g3 input voltage 0.3v to 13v lead temperature (10s max) +300 ? c electrostatic discharge on all pins 2000v min operating conditions relative humidity (non-condensing) 95% eeprom write limits see dc electrical characteristics device operating voltage operating temperature ace8001 2.2 to 5.5v 0 c to 70 c ace8001e 2.2 to 5.5v -40 c to +85 c ACE8000 2.2 to 5.5v 0 c to 70 c ACE8000e 2.2 to 5.5v -40 c to +85 c
4 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex) for low power applications ace8001 dc electrical characteristics v cc = 2.2 to 5.5v all measurements valid for ambient operating temperature unless otherwise stated. 3 i cc active current is dependent on the program code. 4 based on a continuous idle looping program. symbol parameter conditions min typ max units i cc 3 supply current no data eeprom write in progress -40 c to +85 c 2.2v 2.7v 3.3v 5.5v 0.4 0.7 1.2 3.7 1.0 1.2 2.0 6.0 ma ma ma ma i cch halt mode current 3.3v @ -40 c to +85 c 100 5000 na 5.5v @ -40 c to +85 c 0.7 25 a i ccl 4 idle mode current 3.3v 5.5v 120 140 200 350 a a v ccw eeprom write voltage code eeprom in programming mode 4.5 5.0 5.5 v data eeprom in operating mode 2.4 5.5 v s vcc power supply slope 1s/v 10ms/v v il input low with schmitt trigger buffer v cc = 2.2 -5.5v 0.2v cc v v ih input high with schmitt trigger buffer v cc = 2.2v v cc > 2.2v 0.9v cc 0.8v cc v v i ip input pull-up current v cc =5.5v, v in =0v 30 65 350 a i tl tri-state leakage v cc =5.5v 2 200 na v ol output low voltage v cc = 2.2v 3.3v g0, g1, g2, g4 3.0 ma sink 0.2v cc v g5 5.0 ma sink 0.2v cc v output low voltage v cc = 3.3v 5.5v g0, g1, g2, g4 5.0 ma sink 0.2v cc v g5 10.0 ma sink 0.2v cc v v oh output high voltage v cc = 2.2v 5.5v g0, g1, g2, g4 0.4 ma source 0.8v cc v g5 0.8 ma source 0.8v cc v output high voltage v cc = 3.3v 5.5v g0, g1, g2, g4 0.4 ma source 0.8v cc v g5 1.0 ma source 0.8v cc v
5 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex) for low power applications ace8001 ac electrical characteristics v cc = 2.2 to 5.5v all measurements valid for ambient operating temperature unless otherwise stated. 5 the maximum permissible frequency is guaranteed by design but not 100% tested. 6 the parameter is guaranteed by design but not 100% tested. ace8001 electrical characteristics for programming all data following is valid between 4.5v and 5.5v at ambient temperature. the following characteristics are guaranteed by design but are not 100% tested. see eeprom write time in the ac electrical characteris- tics for de nition of the programming ready time. ace8001 brown-out reset (bor) characteristics v cc = 2.2 to 5.5v parameter conditions min typ max units instruction cycle time from internal clock - setpoint 5.0v at +25 c 0.96 1.0 1.04 s internal clock frequency variation 2.4v to 5.5v at constant temperature 10 % 2.4v to 5.5v at full temperature range -12 +8 % crystal oscillator frequency (note 5) 4 mhz external clock frequency (note 5) 4 mhz eeprom write time 2.5 3 ms internal clock start up time (note 6) 20 s oscillator start up time (note 6) 5 cycles parameter description min max units t hi clock high time 500 dc ns t lo clock low time 500 dc ns t dis shift_in setup time 100 ns t dih shift_in hold time 100 ns t dos shift_out setup time 100 ns t doh shift_out hold time 900 ns t sv1 , t sv2 load supervoltage timing 50 s t load1 , t load2 , t load3 , t load4 load timing 5 s v supervoltage supervoltage level 11.5 12.5 v parameter conditions min typ max units bor voltage threshold variation (blsel = 1) -40 c to +85 c 2.25 v
6 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex) for low power applications 3.0 ac & dc electrical characteristic graphs the graphs in this section are for design guidance and are based on preliminary test data. figure 4: rc oscillator frequency vs. temperature figure 5: internal oscillator frequency (a) v cc = 5.0v 1.000 1.200 1.400 1.600 1.800 2.000 2.200 2.400 2.600 3.3k/82pf 5.6k/100pf 6.8k/100pf avg min max frequency (mhz) resistor & capacitor values [k & pf] 0.600 0.800 1.000 1.200 1.400 1.600 3.3k/82pf 5.6k/100pf 6.8k/100pf avg min max frequency (mhz) (b)v cc =2.5v resistor & capacitor values [k & pf] 0.880 0.900 0.920 0.940 0.960 0.980 1.000 1.020 1.040 -45c -20c 0c 25c 85c 125c temperature ( c) frequency (mhz) 2.4 v 3.0 v 3.3 v 3.6 v 4.0 v 4.5 v 5.0 v 5.5 v
7 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications figure 6: lbd and bor threshold levels level 1 level 2 level 3 level 4 level 5 level 6 level 7 level 8 lbd volta g e levels vs. temperatur e v olta g e (v) bor volta g e level vs. temperatur e v olta g e (v) tem p erature [ 2.00 2.20 2.4 0 2. 60 2. 80 3 . 00 3 .2 0 3.40 3.60 3.80 4.00 -45c 0c 25c 85c 125c 1.90 2.00 2.10 2.2 0 2. 30 2.4 0 2 . 50 2.60 2.70 -45c 0c 2 5c 85c 125c bor level
8 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications figure 7: i cc active current tem p erature [ 0.00 0.50 1. 00 1. 50 2. 00 2. 50 3 . 00 3 . 50 4. 00 4. 50 -45 0 2 5 85 125 tem p erature [ -45 0 2 5 85 125 2.2v 2.7v 3.3v 5.0v 5.5v 0.00 2.00 4. 00 6 . 00 8 . 00 1 0 . 00 12 . 00 2.2v 2.7v 3.3v 5.0v 5.5v
9 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications figure 8: halt mode currents figure 9: idle mode current tem p erature [ 0.000 2. 000 4. 000 6 . 000 8 . 000 1 0 . 000 12.000 -45c 0c 2 5c 85c 125c 5.5 v 5.0 v 3.3 v tem p erature [ -45 85 2 5 0 125 0.00 2 0 . 00 4 0 . 00 60 . 00 80 . 00 1 00 . 00 12 0 . 00 140.00 160.00 2.2v 2.7v 3.3v 5.0v 5.5v
10 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications figure 10: vol/voh current ( ma ) vol vs. iol ( g5 @ 2 5 0 . 00 0 .2 0 0 . 40 0 . 60 0 . 80 1. 00 1.2 0 1.4 0 0 . 00 0 2 5 8 15 0 2 5 8 1 5 0 .1 0 0 .2 0 0 . 30 0 .4 0 0 . 50 0 . 60 0 .7 0 0 . 80 2.2v 2.7v 2.2v 2.7v 3.3v 3.6v 5.5v 2.2v 2.7v 2.2v 2.7v 3.3v 3.6v 5.5v volta g e (v) current ( ma ) current ( ma ) 0 0 . 2 0 . 4 0 . 5 0 . 8 1 1.2 0 0 . 2 0 . 4 0 . 5 0 . 8 1 1.2 current ( ma ) v olta g e (v) 0 . 00 0 . 50 1. 00 1. 50 2. 00 2. 50 3 . 00 3 . 50 4. 00 4. 50 5 . 00 5 . 50 6 . 00 1.00 1.50 2. 00 2. 50 3 . 00 3 . 50 4. 00 4. 50 5 . 00 5 . 50 6 . 00 voh vs. ioh ( g0 - g 4 @ 2 5
ace8001 product family arithmetic controller engine (acex ) for low power applications 11 www.fairchildsemi.com ace8001 product family rev. b.2 4.0 arithmetic controller core the acex microcontroller core is speci cally designed for low cost applications involving bit manipulation, shifting and arith- metic operations. it is based on a modi ed harvard architecture meaning peripheral, i/o, and ram locations are addressed sep- arately from instruction data. the core differs from the traditional harvard architecture by aligning the data and instruction memory sequentially. this allows the x-pointer (11-bits) to point to any memory location in either segment of the memory map. this modi cation improves the overall code ef ciency of the core and takes advantage of the exibility found on von neumann style machines. 4.1 cpu registers the acex microcontroller has ve general-purpose registers. these registers are the accumulator (a), x-pointer (x), pro- gram counter (pc), stack pointer (sp), and status register (sr). the x, sp, and sr registers are all memory-mapped. figure 11: programming model 8-bit accumulator register 11-bit x pointer register 10-bit program counter 4-bit stack pointer 8-bit status register negative flag half carry flag (from bit 3) carry flag (from msb) zero flag global interrupt mask ready flag (from eeprom) a x pc sp sr 0 0 0 0 n h c z g 0 0 r 7 10 9 3
ace8001 product family arithmetic controller engine (acex ) for low power applications 12 www.fairchildsemi.com ace8001 product family rev. b.2 4.1.1 accumulator (a) the accumulator is a general-purpose 8-bit register that is used to hold data and results of arithmetic calculations or data manip- ulations. 4.1.2 x-pointer (x) the x-pointer register allows for an 11-bit indexing value to be added to an 8-bit offset creating an effective address used for reading and writing between the entire memory space. (soft- ware can only read from code eeprom.) this provides soft- ware with the exibility of storing lookup tables in the code eeprom memory space for the core s accessibility during nor- mal operation. the x register is divided into two sections. the 10 least signi - cant bits (lsb) of the register is the address of the program or data memory space. the most signi cant bit (msb) of the regis- ter is write only and selects between the data (0x000 to 0x0ff) or program (0xc00 to 0xfff) memory space. example: if bit 10 = 0, then the ld a, [00,x] instruction will take a value from address range 0x000 to 0x0ff and load it into a. if bit 10 = 1, then the ld a, [00,x] instruction will take a value from address range 0xc00 to 0xfff and load it into a. 4.1.3 program counter (pc) the 10-bit program counter register contains the address of the next instruction to be executed. after a reset, if in normal mode the program counter is initialized to 0xc00. 4.1.4 stack pointer (sp) the acex microcontroller has an automatic program stack with a 4-bit stack pointer. the stack can be initialized to any location between addresses 0x30-0x3f. after a reset, the stack pointer is defaulted to 0xf pointing to address 0x3f. normally, the stack pointer is initialized by one of the rst instructions in an applica- tion program. the stack is con gured as a data structure which decrements from high to low memory. each time a new address is pushed onto the stack, the core decrements the stack pointer by two. each time an address is pulled from the stack, the core incre- ments the stack pointer by two. at any given time, the stack pointer points to the next free location in the stack. when a subroutine is called by a jump to subroutine (jsr) instruction, the address of the instruction is automatically pushed onto the stack least signi cant byte rst. when the sub- routine is nished, a return from subroutine (ret) instruction is executed. the ret instruction pulls the previously stacked return address from the stack and loads it into the program counter. execution then continues at the recovered return address. 4.1.5 status register (sr) this 8-bit register contains four condition code indicators (c, h, z, and n), an interrupt masking bit (g), and an eeprom write ag (r). the condition code indicators are automatically updated by most instructions. (see table 8) carry/borrow (c) the carry ag is set if the arithmetic logic unit (alu) performs a carry or borrow during an arithmetic operation and by its dedi- cated instructions. the rotate instruction operates with and through the carry bit to facilitate multiple-word shift operations. the ldc and invc instructions facilitate direct bit manipulation using the carry ag. half carry (h) the half carry ag indicates whether an over ow has taken place on the boundary between the two nibbles in the accumu- lator. it is primarily used for binary coded decimal (bcd) arith- metic calculation. zero (z) the zero ag is set if the result of an arithmetic, logic, or data manipulation operation is zero. otherwise, it is cleared. figure 12: basic interrupt structure t1pnd t0pnd wkpnd t1en t0int en wkint en g intr t1 t0 miw interrupt pending flags interrupt enable bits global interrupt enable interrupt interrupt source with priority
ace8001 product family arithmetic controller engine (acex ) for low power applications 13 www.fairchildsemi.com ace8001 product family rev. b.2 negative (n) the negative ag is set if the msb of the result from an arith- metic, logic, or data manipulation operation is set to one. other- wise, the ag is cleared. a result is said to be negative if its msb is a one. interrupt mask (g) the interrupt request mask (g) is a global mask that disables all maskable interrupt sources. if the g bit is cleared, interrupts can become pending, but the operation of the core continues uninterrupted. however, if the g bit is set an interrupt is recog- nized. after any reset, the g bit is cleared by default and can only be set by a software instruction. when an interrupt is rec- ognized, the g bit is cleared after the pc is stacked and the interrupt vector is fetched. once the interrupt is serviced, a return from interrupt instruction is normally executed to restore the pc to the value that was present before the interrupt occurred. the g bit is the reset to one after a return from inter- rupt is executed. although the g bit can be set within an inter- rupt service routine, nesting interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. 4.2 interrupt handling when an interrupt is recognized, the current instruction com- pletes its execution. the return address (the current value in the program counter) is pushed onto the stack and execution con- tinues at the address speci ed by the unique interrupt vector (see table 9). this process takes ve instruction cycles. at the end of the interrupt service routine, a return from interrupt (reti) instruction is executed. the reti instruction causes the saved address to be pulled off the stack in reverse order. the g bit is set and instruction execution resumes at the return address. the acex microcontroller is capable of supporting four inter- rupts. three are maskable through the g bit of the sr and the fourth (software interrupt) is not inhibited by the g bit (see fig- ure 12). the software interrupt is generated by the execution of the intr instruction. once the intr instruction is executed, the acex core will interrupt whether the g bit is set or not. the intr interrupt is executed in the same manner as the other maskable interrupts where the program counter register is stacked and the g bit is cleared. this means, if the g bit was enabled prior to the software interrupt the reti instruction must be used to return from interrupt in order to restore the g bit to its previous state. however, if the g bit was not enabled prior to the software interrupt the ret instruction must be used. in case of multiple interrupts occurring at the same time, the acex microcontroller core has prioritized the interrupts. the interrupt priority sequence in shown in table 6. 4.3 addressing modes the acex microcontroller has six addressing modes indexed, direct, immediate, absolute jump, and relative jump. indexed the instruction allows an 8-bit unsigned offset value to be added to the 10-lsbs of the x-pointer yielding a new effective address. this mode can be used to address any memory space (program or data). direct the instruction contains an 8-bit address eld that directly points to the data memory space as an operand. immediate the instruction contains an 8-bit immediate eld as an operand. inherent this instruction has no operands associated with it. absolute the instruction contains a 10-bit address that directly points to a location in the program memory space. there are two operands associated with this addressing mode. each operand contains a byte of an address. this mode is used only for the long jump (jmp) and jsr instructions. relative this mode is used for the short jump (jp) instructions where the operand is a value relative to the current pc address. with this instruction, software is limited to the number of bytes it can jump, -31 or +32. table 6: interrupt priority sequence priority (4 highest, 1 lowest) interrupt 4 miw (edgei) 3 timer0 (tmri0) 2 timer1 (tmri1) 1 software (intr)
14 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications table 7: instruction addressing modes instruction immediate direct indexed inherent relative absolute adc and subc xor a, # a, # a, # a, # a, m a, m a, m a, m clr inc dec m m m a a a x x ifeq ifgt ifne a, # a, # a, # m,# a, m a, m a, m sc rc ifc ifnc invc ldc stc #, m #, m no-op no-op no-op no-op no-op rlc rrc a a ld st ld a, # m, # x, # a, m a, m m, m a, [00,x] a, [00,x] nop no-op ifbit sbit rbit #, m #, m #, m jp jsr jmp ret reti intr no-op no-op no-op rel m m
ace8001 product family arithmetic controller engine (acex ) for low power applications 15 www.fairchildsemi.com ace8001 product family rev. b.2 table 8: instruction cycles and bytes mnemonic operand bytes cycles flags affected adc a, # 2 2 c,h,z,n adc a, m 2 2 c,h,z,n and a, # 2 2 z,n and a, m 2 2 z,n clr a 1 1 z,n,c,h clr m 2 1 z,n,c,h dec a 1 1 z,n dec m 2 2 z,n dec x 1 1 z ifbit #, m 2 2 none ifc 1 1 none ifeq a, # 2 2 none ifeq a, m 2 2 none ifeq m, # 3 3 none ifgt a, # 2 2 none ifgt a, m 2 2 none ifne a, # 2 2 none ifne a, m 2 2 none ifnc 1 1 none inc a 1 1 z,n inc m 2 2 z,n inc x 1 1 z intr 1 5 none invc 1 1 c jmp m 3 4 none mnemonic operand bytes cycles flags affected jp 1 1 none jsr m 3 5 none ld a, # 2 2 none ld a, [00,x] 2 3 none ld a, m 2 2 none ld m, # 3 3 none ld m, m 3 3 none ld x, # 3 3 none ldc #, m 2 2 c nop 1 1 none rbit #, m 2 2 z,n rc 1 1 c,h ret 1 5 none reti 1 5 none rlc a 1 1 c,z,n rrc a 1 1 c,z,n sbit #, m 2 2 z,n sc 1 1 c,h st a, [00,x] 2 3 none st a, m 2 2 none stc #, m 2 2 z,n subc a, # 2 2 c,h,z,n subc a, m 2 2 c,h,z,n xor a, # 2 2 z,n xor a, m 2 2 z,n
16 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications 4.4 memory map all i/o ports, peripheral registers and core registers (except the accumulator and the program counter) are mapped into memory space. table 9: memory map address memory space block contents 0x00 - 0x3f data sram data ram 0x40 - 0x7f data eeprom data eeprom 0xaa data timer1 t1ra register 0xab, 0xad reserved 0xac data timer1 tmr1 register 0xae data timer1 t1cntrl register 0xaf data miw wkedg register 0xb0 data miw wkpnd register 0xb1 data miw wken register 0xb2 data i/o portgd register 0xb3 data i/o portgc register 0xb4 data i/o portgp register 0xb5 data timer0 wdsvr register 0xb6 data timer0 t0cntrl register 0xb7 data clock halt mode register 0xb8 - 0xba reserved 0xbb data init. reg. initialization register 1 0xbc data init. reg. initialization register 2 0xbd data lbd lbd register 0xbe data core xhi register 0xbf data core xlo register 0xc0 data clock power mode clear (pmc) register 0xce data core sp register 0xcf data core status register (sr) 0xc00 - 0xff5 program eeprom code eeprom 0xff6 - 0xff7 program core timer0 interrupt vector 0xff8 - 0xff9 program core timer1 interrupt vector 0xffa - 0xffb program core miw interrupt vector 0xffc - 0xffd program core soft interrupt vector 0xffe - 0xfff reserved
ace8001 product family arithmetic controller engine (acex ) for low power applications 17 www.fairchildsemi.com ace8001 product family rev. b.2 4.5 memory the acex microcontroller device has 64 bytes of sram and 64 bytes of eeprom available for data storage. the device also has 1k bytes of eeprom for program storage. software can read and write to sram and data eeprom but can only read from the code eeprom. while in normal mode, the code eeprom is protected from any writes. the code eeprom can only be rewritten when the device is in program mode and if the write disable (wdis) bit of the initialization register is not set to 1. while in normal mode, the user can write to the data eeprom array by 1) polling the ready (r) ag of the sr, then 2) execut- ing the appropriate instruction. if the r ag is 1, the data eeprom block is ready to perform the next write. if the r ag is 0, the data eeprom is busy. the data eeprom array will reset the r ag after the completion of a write cycle. attempts to read, write, or enter halt/idle mode while the data eeprom is busy (r = 0) can affect the current data being written. 4.6 initialization registers the acex microcontroller has two 8-bit wide initialization regis- ters. these registers are read from the memory space on power-up to initialize certain on-chip peripherals. figure 13 pro- vides a detailed description of initialization register 1. the ini- tialization register 2 is used to trim the internal oscillator to its appropriate frequency. this register is pre-programmed in the factory to yield an internal instruction clock of 1mhz. both initialization registers 1 and 2 can be read from and writ- ten to during programming mode. however, re-trimming the internal oscillator (writing to the initialization register 2) once it has left the factory is discouraged . figure 13: initialization register 1 (0) rdis 8,9 if set, disables attempts to read the contents from the eeproms while in programming mode (1) wdis 8,9 if set, disables attempts to write new contents to the eeproms while in programming mode (2) ubd 8,9 if set, the device will not allow any writes to occur in the upper block of data eeprom (0x60-0x7f) (3) blsel 7 if set, the brown-out reset (bor) voltage reference level is set to its higher range for the ace8001 if not set, the bor voltage reference level is set to its lower range (4) boren if set, allows a bor to occur if v cc falls below the voltage reference level (5) wden if set, enables the on-chip processor watchdog circuit (6) cmode[1] clock mode select bit 1 (see table 13) (7) cmode[0] clock mode select bit 0 (see table 13) 7 the blsel bit is set to its appropriate level in the factory. if writing to the initialization register is necessary, be sure t o maintain bits set value. 8 if both the wdis and rdis bits are set, the device will no longer be able to be placed into program mode. 9 if the rdis or ubd bits are not set while the wdis bit is not set, then the rdis and ubd bits can be reset. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmode[0:1] wden boren blsel 7 ubd 8,9 wdis 8,9 rdis 8,9
ace8001 product family arithmetic controller engine (acex ) for low power applications 18 www.fairchildsemi.com ace8001 product family rev. b.2 5.0 timer 1 timer 1 is a versatile 8-bit timer. its main function is to operate as a pulse width modulation (pwm) generator that generates pulses of a speci ed width and duty cycles. timer 1 contains an 8-bit timer register (tmr1), an 8-bit auto- reload register (t1ra), and an 8-bit control register (t1cntrl). all registers are memory-mapped for simple access through the core. for the pwm signal generation the timer contains an output (t1) that is multiplexed with the i/o pin g2. the timer can be started or stopped through the t1cntrl reg- ister bit t1c0. when running, the timer counts down (decre- ments) every clock cycle. the timer s clock has a pre-scalar and is selectable through two t1cntrl register bits t1psc[1:0]. depending on the selected operating mode, occurrences of timer under ow (transitions from 0x00 to 0xff or reload) can either generate an interrupt and/or toggle the t1 output pin. timer 1 s interrupt (tmri1) can be enabled by the interrupt enable (t1en) bit in the t1cntrl register. when the timer interrupt is enabled, the source of the interrupt is a timer under- ow. by default, the timer register is reset to 0xff and the auto- reload register is reset to 0x00. 5.1 timer control bits reading and writing to the t1cntrl register controls the timer s operation. by writing to the control bits, the user can enable or disable the timer interrupts, set the mode of operation, start or stop the timer, and select the clock. the t1cntrl reg- ister bits are described in table 10. table 10: timer1 control register bits t1cntrl register name function bit 7 ----------- reserved bit 6 ----------- reserved bit 5 t1c1 t1 toggle enable bit: 1 = t1 toggle enabled, 0 = t1 toggle disabled bit 4 t1c0 tmr1 run: 1 = start timer, 0 = stop timer bit 3 t1pnd timer1 interrupt pending ag: 1 = timer1 interrupt pending, 0 = timer1 interrupt not pending bit 2 t1en timer1 interrupt enable bit: 1 = timer1 interrupt enabled, 0 = timer1 interrupt disabled bit 1,0 t1psc pre-scalar selection bits: selects the 1mhz clock divider to be by 1 (00b), 2 (01b), 4 (10b), or 8 (11b)
ace8001 product family arithmetic controller engine (acex ) for low power applications 19 www.fairchildsemi.com ace8001 product family rev. b.2 5.2 pulse width modulation (pwm) mode in the pwm mode, the timer counts down at the instruction clock rate. when an under ow occurs, the timer register is reloaded from t1ra and the count down proceeds from the loaded value. at every under ow, a pending ag (t1pnd) located in the t1cntrl register is set. software must then clear the t1pnd ag and load the t1ra register with an alter- nate pwm value. in addition, the timer can be con gured to tog- gle the t1 output bit upon under ow. con guring the timer to toggle t1 results in the generation of a signal outputted from port g2 with the width and duty cycle controlled by the values stored in the t1ra. a block diagram of the timer s pwm mode of operation is shown in figure 14. the timer has one interrupt (tmri1) that is maskable through the t1en bit of the t1cntrl register. however, the core is only interrupted if the t1en bit and the g (global interrupt enable) bit of the sr is set. if interrupts are enabled, the timer will gen- erate an interrupt each time t1pnd ags is set (whenever the timer under ows provided that the pending ag was cleared.) the interrupt service routine is responsible for proper handling of the t1pnd ag and the t1en bit. the interrupt will be synchronous with every rising and falling edge of the t1 output signal. generating interrupts only on ris- ing or falling edges of t1 is achievable through appropriate han- dling of the t1en bit or t1pnd ag through software. the following steps show how to properly con gure timer 1 to operate in the pwm mode. for this example, the t1 output sig- nal is toggled with every timer under ow and the high and low times for the t1 output can be set to different values. the t1 output signal can start out either high or low depending on the con guration of i/o g2; the instructions below are for start- ing with the t1 output high. follow the instructions in parenthe- ses to start the t1 output low. 1. con gure t1 as an output by setting bit 2 of portgc. - sbit 2, portgc ; con gure g2 as an output 2. initialize t1 to 1 (or 0) by setting (or clearing) bit 2 of portgd. - sbit 2, portgd ; set g2 high 3. load the initial pwm high (low) time into the timer register. - ld tmr1, #6fh ; high (low) for .444ms (1mhz/4 clock) 4. load the pwm low (high) time into the t1ra register. - ld t1ra, #2fh ; low (high) for .188ms (1mhz/4 clock) 5. write the appropriate control value to the t1cntrl register to select pwm mode with t1 toggle, to select the divide by 4 pre-scalar, and to clear the enable and pending ags. (see table 12) - ld t1cntrl, #22h ; setting the t1c0 bit starts the timer 6. set the t1co bit to start the timer. - sbit t1cp, t1cntrl ; t1co equals 4 7. after every under ow, load t1ra with alternate values. if the user wishes to generate an interrupt on timer output transi- tions, reset the pending ags and then enable the interrupt using t1en. the g bit must also be set. the interrupt ser- vice routine must reset the pending ag and perform what- ever processing is desired. - rbit t1pnd, t1cntrl ; t1pnd equals 3 - ld t1ra, #6fh ; low for .444ms (1mhz/4 clock) figure 14: pulse width modulation mode data bus 8-bit auto-reload register (t1ra) 8-bit timer (tmr1) data latch t1 underflow interrupt instruction clock t1psc[1:0] 0 sel 1 2 3 8 4 2
ace8001 product family arithmetic controller engine (acex ) for low power applications 20 www.fairchildsemi.com ace8001 product family rev. b.2 6.0 timer 0 timer 0 is a 12-bit free running idle timer. upon power-up or any reset, the timer is reset to 0x000 and then counts up continu- ously based on the instruction clock of 1mhz (1 s). software cannot read from or write to this timer. however, software can monitor the timer s pending (t0pnd) bit that is set every 8192 cycles (initially 4096 cycles after a reset or after the watchdog has been- serviced). the t0pnd ag is set every other time the timer over ows (transitions from 0xfff to 0x000). after an over- ow, the timer will reset and restart its counting sequence. software can either poll the t0pnd bit or vector to an interrupt subroutine. in order to interrupt on a t0pnd, software must be sure to enable the timer 0 interrupt enable (t0inten) bit in the timer 0 control (t0cntrl) register and also make sure the g bit is set in sr. once the timer interrupt is serviced, software should reset the t0pnd bit before exiting the routine. timer 0 supports the following functions: 1. exiting from idle mode (see section 16.0 for details.) 2. start up delay from halt mode 3. watchdog pre-scalar (see section 7.0 for details.) the t0inten bit is a read/write bit. if set to 0, interrupt requests from the timer 0 are ignored. if set to 1, interrupt requests are accepted. upon reset, the t0inten bit is reset to 0. the t0pnd bit is a read/write bit. if set to 1, it indicates that a timer 0 interrupt is pending. this bit is set by a timer 0 over ow and is reset by software or system reset. the wkinten bit is used in the multi-input wakeup/interrupt block. see section 8.0 for details. 7.0 watchdog the watchdog timer is used to reset the device and safely recover in the rare event of a processor runaway condition. the 12-bit timer 0 is used as a pre-scalar for watchdog timer. the watchdog timer must be serviced before every 61,440 cycles but no sooner than 4096 cycles since the last watchdog reset. the watchdog is serviced through software by writing the value 0x1b to the watchdog service (wdsvr) register (see figure 16). the part resets automatically if the watchdog is ser- viced too frequent, or not frequent enough. the watchdog timer must be enabled through the watchdog enable bit (wden) in the initialization register. the wden bit can only be set while the device is in programming mode. once set, the watchdog will always be powered-up enabled. software cannot disable the watchdog. the watchdog timer can only be disabled in programming mode by resetting the wden bit as long as the memory write protect (wdis) feature is not enabled. warning ensure that the watchdog timer has been serviced before entering idle mode because it remains operational during this time. figure 15: timer 0 control register de nition (t0cntrl) figure 16: watchdog server register (wdsvr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wkintenxxxxx t0pnd t0en bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00011011
ace8001 product family arithmetic controller engine (acex ) for low power applications 21 www.fairchildsemi.com ace8001 product family rev. b.2 8.0 multi-input wakeup/interrupt block the multi-input wakeup (miw)/interrupt contains three mem- ory-mapped registers associated with this circuit: wkedg (wakeup edge), wken (wakeup enable), and wkpnd (wakeup pending). each register has three bits with each bit corresponding to an input pins as shown in figure 17. all three registers are initialized to zero upon reset. the wkedg register establishes the edge sensitivity for each of the wake-up input pin: either (0) rising edge or (1) falling edge. the wken register enables (1) or disables (0) each of the port pins for the wakeup/interrupt function. the wakeup i/os used for the wakeup/interrupt function must also be con gured as an input pin in its associated port con guration register. however, an interrupt (edge1) of the core will not occur unless interrupts are enabled for the block via bit 7 of the t0cntrl register (see figure 15) and the g (global interrupt enable) bit of the sr is set. the wkpnd register contains the pending ags corresponding to each of the port pins (1 for wakeup/interrupt pending, 0 for wakeup/interrupt not pending). to use the multi-input wakeup/interrupt circuit, perform the steps listed below. performing the steps in the order shown will prevent false triggering of a wakeup/interrupt condition. this same procedure should be used following any type of reset because the wakeup inputs are left oating after resets resulting in unknown data on the port inputs. 1. clear the wken register. -clr wken 2. if necessary, write to the port con guration register to select the desired port pins to be con gured as inputs. -rbit 4, portgc ;g3, g4, and/or g5 3. if necessary, write to the port data register to select the desired port pins input state. -sbit 4, portgd ;pull-up 4. write the wkedg register to select the desired type of edge sensitivity for each of the pins used. -ld wkedg, #38h ;falling edges 5. clear the wkpnd register to cancel any pending bits. -clr wkpnd 6. set the wken bits associated with the pins to be used, thus enabling those pins for the wakeup/interrupt function. -ld wken, #38h ;enabling g3, g4, g5 once the multi-input wakeup/interrupt function has been con g- ured, a transition sensed on any of the enabled pins will set the corresponding bit in the wkpnd register. the wkpnd bits can bring the device out of the halt/idle mode and can also trigger an interrupt if the interrupt is enabled. the interrupt service routine can read the wkpnd register to determine which pin sensed the interrupt. the interrupt service routine or other software should clear the pending bit. the device will not enter halt/idle mode as long as a wkpnd pending bit is pending and enabled. the user has the responsibility of clearing the pending ags before attempting to enter the halt/idle mode. upon reset, the wkedg register is con gured to select positive- going edge sensitivity for all wakeup inputs. if the user wishes to change the edge sensitivity of a port pin, use the following proce- dure to avoid false triggering of a wakeup/interrupt condition. 1. clear the wken bit associated with the pin to disable that pin. 2. write the wkedg register to select the new type of edge sensi- tivity for the pin. 3. clear the wkpnd bit associated with the pin. 4. set the wken bit associated with the pin to re-enable it. portg provides the user with three fully selectable, edge sensi- tive interrupts that are all vectored into the same service subrou- tine. the interrupt from portg shares logic with the wakeup circuitry. the wken register allows interrupts from portg to be individually enabled or disabled. the wkedg register speci es the trigger condition to be either a positive or a negative edge. the wkpnd register latches in the pending trigger conditions. since portg is also used for exiting the device from the halt/ idle mode, the user can elect to exit the halt/idle mode either with or without the interrupt enabled. if the user elects to disable the interrupt, then the device restarts execution from the point at which it was stopped ( rst instruction cycle of the instruction follow- ing halt/idle mode entrance instruction). in the other case, the device nishes the instruction that was being executed when the part was stopped and then branches to the interrupt service rou- tine. the device then reverts to normal operation. figure 17: miw register bit assignments figure 18: multi-input wakeup (miw) block diagram bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x g5 g4 g3 x x x 10 wkinten: bit 7 of t0cntr data bus 5 3 wken[5:3] 3 5 wkedg[3:5] wkpnd[3:5] g5 g3 edgei wkout 4 4 g4 wkinten 10
ace8001 product family arithmetic controller engine (acex ) for low power applications 22 www.fairchildsemi.com ace8001 product family rev. b.2 9.0 i/o port the six i/o pins are bi-directional with the exception of g3 which is always an input with weak pull-up (see figure 19). the bi-directional i/o pins can be individually con gured by software to operate as high-impedance inputs, as inputs with weak pull- up, or as push-pull outputs. the operating state is determined by the contents of the corresponding bits in the data and con g- uration registers. each bi-directional i/o pin can be used for general purpose i/o, or in some cases, for a speci c alternate function determined by the on-chip hardware. 9.1 i/o registers the i/o pins (g0-g5) have three memory-mapped port regis- ters associated with the i/o circuitry: a port con guration regis- ter (portgc), a port data register (portgd), and a port input register (portgp). portgc is used to con gure the pins as inputs or outputs. a pin may be con gured as an input by writing a 0 or as an output by writing a 1 to its corresponding portgc bit. if a pin is con gured as an output, its portgd bit repre- sents the state of the pin (1 = logic high, 0 = logic low). if the pin is con gured as an input, its portgd bit selects whether the pin is a weak pull-up or a high-impedence input. table 11 pro- vides details of the port con guration options. the port con gu- ration and data registers are both read/writable. reading portgp returns the value of the port pins regardless of how the pins are con gured. since this device supports multi-input wakeup/interrupt, the portg inputs have schmitt triggers. figure 19: portgd logic diagram figure 20: i/o register bit assignments table 11: i/o con guration options 11 g3 is only an input 12 g5 is not available on soic-8 package with the reset pin option (ACE8000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxg5 12 g4 g3 11 g2 g1 g0 con guration bit data bit port pin con guration 0 0 high-impedence input (tri-state input) 0 1 input with pull-up (weak one input) 1 0 push-pull zero output 1 1 push-pull one output weak pull-up control portgc portgd portgp pin gx
ace8001 product family arithmetic controller engine (acex ) for low power applications 23 www.fairchildsemi.com ace8001 product family rev. b.2 10.0 in-circuit programming speci cation 13,14 the acex microcontroller supports in-circuit programming of the internal data eeprom, code eeprom, and the initializa- tion registers. an externally controlled four wire interface consisting of a load control pin (g3), a serial data shift-in input pin (g4), a serial data shift-out output pin (g2), and a clock pin (g1) is used to access the on-chip memory locations. communication between the acex microcontroller and the external programmer is made through a 32-bit command and response word described in table 12. the serial data timing for the four-wire interface is shown in fig- ure 22 and the programming protocol is shown in figure 21. 10.1 write sequence the external programmer brings the acex microcontroller into programming mode by applying a super voltage level to the load pin. the external programmer then needs to set the load pin to 5v before shifting in the 32-bit serial command word using the shift_in and clock signals. by de nition, bit 31 of the command word is shifted in rst. at the same time, the acex microcontroller shifts out the 32-bit serial response to the last command on the shift_out pin. it is recommended that the external programmer samples this signal t access (1s) after the rising edge of the clock signal. the serial response word, sent immediately after entering programming mode, contains indeterminate data. after 32 bits have been shifted into the device, the external pro- grammer must set the load signal to 0v, and then apply two clock pulses as shown in figure 21 to complete program cycle. the shift_out pin acts as the handshaking signal between the device and programming hardware once the load signal is brought low. the device sets shift_out low by the time the programmer has sent the second rising edge during the load = 0v phase (if the timing speci cations in figure 21 are obeyed). the device will set the r bit of the status register when the write operation has completed. the external programmer must wait for the shift_out pin to go high before bringing the load sig- nal to 5v to initiate a normal command cycle. 10.2 read sequence when reading the device after a write, the external programmer must set the load signal to 5v before it sends the new com- mand word. next, the 32-bit serial command word (for during a read) should be shifted into the device using the shift_in and the clock signals while the data from the previous com- mand is serially shifted out on the shift_out pin. after the read command has been shifted into the device, the external programmer must, once again, set the load signal to 0v and apply two clock pulses as shown in figure 21 to complete read cycle. data from the selected memory location, will be latched into the lower 8 bits of the command word shortly after the second rising edge of the clock signal. writing a series of bytes to the device is achieved by sending a series of write command words while observing the devices handshaking requirements. reading a series of bytes from the device is achieved by send- ing a series of read command words with the desired addresses in sequence and reading the following response words to verify the correct address and data contents. the addresses of the data eeprom and code eeprom loca- tions are the same as those used in normal operation. powering down the device will cause the part to exit program- ming mode. table 12: 32-bit command and response word 13 application note reference: how to in-circuit program the acex family of microcontrollers. 14 during in-circuit programming, g5 must be either not connected or driven high. bit number input command word output response word bits 31 30 must be set to 0 x bit 29 set to 1 to read/write data eeprom, or the initializa- tion registers, otherwise 0 x bit 28 set to 1 to read/write code eeprom, otherwise 0 x bits 27 25 must be set to 0 x bit 24 set to 1 to read, 0 to write x bits 23 18 must be set to 0 x bits 17 8 address of the byte to be read or written same as input command word bits 7 0 data to be programmed or zero if data is to be read programmed data or data read at speci ed address
24 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications figure 21: programming protocol 13 figure 22: serial data timing load (g3) clock (g1) shift_in (g4) shift_out (g2) (in write mode) bit 31 bit 30 bit 0 bit 31 shift_out (g2) (in read mode) t sv1 t sv2 a a: start of programming cycle 32 clock pulses t load2 busy ready a t load4 t load3 t ready busy low by 2nd clock pulse enter prog. mode t load1 valid valid shift_in (g4) clock (g1) t hi t lo t dis t dih t dos t doh t access shift_out (g2)
ace8001 product family arithmetic controller engine (acex ) for low power applications 25 www.fairchildsemi.com ace8001 product family rev. b.2 11.0 brown-out/low battery detect circuit the brown-out reset (bor) and low battery detect (lbd) cir- cuits on the acex microcontroller have been designed to offer two types of voltage reference comparators. the sections below will describe the functionality of both circuits. 11.1 brown out reset the brown-out reset (bor) function is used to hold the device in reset when v cc drops below a xed threshold. while in reset, the device is held in its initial condition until v cc rises above the threshold value. shortly after v cc rises above the threshold value, an internal reset sequence is started. after the reset sequence, the core fetches the rst instruction and starts nor- mal operation. on the devices, the bor should be used in situations when v cc rises and falls slowly and in situations when v cc does not fall to zero before rising back to operating range. the bor can be thought of as a supplement function to the power-on reset when v cc does not fall below ~1.5v. the power-on reset circuit works best when v cc starts from 0v and rises sharply. so in applications where v cc is not constant, the bor will give added device stability. the bor circuit must be enabled through the bor enable bit (boren) in the initialization register. the boren bit can only be set while the device is in programming mode. once set, the bor will always be powered-up enabled. software cannot dis- able the bor. the bor can only be disabled in programming mode by resetting the boren bit as long as the global write protect (wdis) feature is not enabled. 11.2 low battery detect the low battery detect (lbd) circuit allows software to monitor the v cc level at the lower voltage ranges. lbd has eight soft- ware programmable voltage reference threshold levels ranging from 2.0v (bat_tri[2:0] set to zero) to 3.6v (bat_trim[2:0] set to one) that can be changed on the y. once v cc falls below the selected threshold, the lbd ag in the lbd control register is set. the lbd ag will hold its value until v cc rises above the threshold. (see figure 23) the lbd bit is read only. if lbd is 0, it indicates that the v cc level is higher than the selected threshold. if lbd is 1, it indi- cates that the v cc level is below the selected threshold. the threshold level can be adjusted up to eight levels using the three trim bits (bat_trim[2:0]) of the lbd control register. the lbd ag does not cause any hardware actions or an interruption of the processor. it is for software monitoring only. the lbd function is disabled during halt/idle mode. after exiting halt/idle, software must wait at lease 10s before reading the lbd bit to ensure that the internal circuit has stabi- lized. figure 23: lbd control register de nition figure 24: bor/lbd block diagram 16 see figure 13 for information on blsel. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bat_trim[2:0] 0 x x x lbd 7 6 5 4 3 2 1 0 adjust reference voltage lbd control register + _ + _ to reset logic vcc bor lbd 1 0 s 1.8v 2.2v blsel 16
ace8001 product family arithmetic controller engine (acex ) for low power applications 26 www.fairchildsemi.com ace8001 product family rev. b.2 12.0 reset block when a reset sequence is initiated, all i/o registers will be reset setting all i/os to high-impedence inputs. the system clock is restarted after the required clock start-up delay. a reset is generated by any one of the following three conditions: power-on reset (as described in section 13.0) brown-out reset (as described in section 11.1) watchdog reset (as described in section 7.0) external reset 15 (as described in section 13.0) 13.0 power-on-reset the power-on reset (por) circuit is guaranteed to work if the rate of rise of v cc is no slower than 10ms/1volt. the por circuit was designed to respond to fast low to high transitions between 0v and v cc . the circuit will not work if v cc does not drop to 0v before the next power-up sequence. in applications where 1) the v cc rise is slower than 10ms/1 volt or 2) v cc does not drop to 0v before the next power-up sequence the external reset option should be used. the external reset option provides a way to properly reset the acex microcontroller if por cannot be used in the application. the external reset pin contains an inter- nal pull-up resistor. 14.0 clock the acex microcontroller has an on-board oscillator trimmed to a frequency of 2mhz who is divided down by two yielding a 1mhz frequency.(see ac electrical characteristics.) upon power-up, the on-chip oscillator runs continuously unless enter- ing halt mode or using an external clock source. (see figure 26.) if required, an external oscillator circuit may be used depending on the states of the cmode bits of the initialization register. (see table 13) when the device is driven using an external clock, the clock input to the device (g1/cki) can range between dc to 4mhz. for external crystal con guration, the output clock (cko) is on the g0 pin. if an external crystal or rc is used, to yield the corresponding instruction clock the input frequency is internally divided down by four. if the device is con gured for an external square clock, it will not be divided. table 13: cmode[0:1] bit de nition figure 25: bor and por circuit relationship diagram (see ac electrical characteristics) cmode[0] cmode[1] clock type 0 0 internal 1 mhz clock 1 0 external square clock 1 1 external rc clock v cc (pin 8) bor reset circuit output global reset to logic external reset pin (14-pin only) b a output por (pin 7) output v cc time bor output 1.75 0 v cc v cc 0 por output por output pulse 1.8v 0 v cc v cc 5.0v 0 the reset circuit will trigger when inputs a or b transition from high to low. at that time the global reset signal will go high which will reset all controller logic. the global reset will go high and stay high for around 1 s. 15 available as option on soic-8 package only, it replaces the port g5
ace8001 product family arithmetic controller engine (acex ) for low power applications 27 www.fairchildsemi.com ace8001 product family rev. b.2 figure 26: rc oscillator diagrams 15.0 halt mode the halt mode is a power saving feature that almost com- pletely shuts down the device for current conservation. the device is placed into halt mode by setting the halt enable bit (ehalt) of the halt register through software using only the ld m, # instruction. ehalt is a write only bit and is automati- cally cleared upon exiting halt. when entering halt, the inter- nal oscillator and all the on-chip systems including the lbd and the bor circuits are shut down. the device can exit halt mode only by the miw circuit. there- fore, prior to entering halt mode, software must con gure the miw circuit accordingly. (see section 8.0) after a wakeup from halt, a 64 clock cycle start-up delay is initiated to allow the internal oscillator to stabilize before normal execution resumes. immediately after exiting halt, software must clear the power mode clear (pmc) register by only using the ld m, # instruc- tion. (see figure 28) 16.0 idle mode in addition to the halt mode power saving feature, the device also supports an idle mode operation. the device is placed into idle mode by setting the idle enable bit (eidle) of the halt register through software using only the ld m, # instruc- tion. eidle is a write only bit and is automatically cleared upon exiting idle. the idle mode operation is similar to halt except the internal oscillator, the watchdog, and the timer 0 remain active while the other on-chip systems including the lbd and the bor circuits are shut down. the device can exit idle by a timer 0 over ow every 8192 cycles or/and by the miw circuit. if exiting idle mode with the miw, prior to entering, software must con gure the miw circuit accordingly. (see section 8.0) once a wake from idle mode is triggered, the core will begin normal operation by the next clock cycle. immediately after exiting idle mode, software must clear the power mode clear (pmc) register by using only the ld m, # instruction. (see figure 29) figure 27: halt register de nition figure 28: recommended halt flow figure 29: recommended idle flow c v cc r cki (g1) cko (g0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxxxeidleehalt normal mode ld halt, #01h halt multi-input wakeup ld pmc, #00h resume nor mal mode normal mode idle mode resume normal mode ld pmc, #00h multi-input wakeup ld halt, #01h timer0 overflow
28 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications ordering information part number core type max. # i/os program memory size operating voltage range temperature range package tape and reel 012 6 1k 2k 1.8 5.5v 2.2 5.5v 0 to 70 c -40 to +85c -40 to +125 c 8-pin soic 8-pin tssop ace8001m8 x x x x x x ace8001m8x x x x x x x x ace8001mt8 x x x x x x ace8001mt8x x x x x x x x ace8001em8 x x x x x x ace8001em8x x x x x x x x ace8001emt8 x x x x x x ace8001emt8x x x x x x x x ACE8000m8 x x x x x x ACE8000m8x x x x x x x x ACE8000em8 x x x x x x ACE8000em8x x x x x x x x
29 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications physical dimensions inches (millimeters) unless otherwise noted molded small out-line package (m8) order number ace8001m8/ace8001em8/ACE8000m8/ACE8000em8 package number m08a 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.004 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
30 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications physical dimensions inches (millimeters) unless otherwise noted 8-pin molded tssop (mt8) order number ace8001mt8/ace8001emt8 package number mtc08 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0118 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
31 www.fairchildsemi.com ace8001 product family rev. b.2 ace8001 product family arithmetic controller engine (acex ) for low power applications life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 acex development tools general information fairchild semiconductor offers different possibilities to evaluate and emulate software written for acex. simulator: is a windows program able to load, assemble, and debug acex programs. it is possible to place as many breakpoints as needed, trace the program execution in symbolic format, and program a device with the proper options. the acex simulator is available free-of-charge and can be downloaded from fairchild s web site at www .f airchildsemi.com/products/micro acex emulator kit: fairchild also offers a low cost real-time in- circuit emulator kit that includes: emulator board emulator software assembler and manuals power supply dip14 target cable pc cable the acex emulator allows for debugging the program code in a symbolic format. it is possible to place one breakpoint and watch various data locations. it also has built-in programming capability. prototype board kits: fairchild offer two solutions for the sim- pli cation of the breadboard operation so that acex applica- tions can be quickly tested. 1) acedemo is can be used for general purpose applications 2) acetxrx for transmitting / receiving (rf, ir, rs232, rs485) applications. acedemo has 8 switches, 8 leds, rs232 voltage translator, buzzer, and a lamp with a small breadboard area. ordering p/ns programming adapters: dip8 - aceadaptn dip14 - aceadaptn14 tssop8 - aceadaptmt8 so8 - aceadaptm8 so14 - aceadaptm emulator kit: aceice (110vac) aceiceeu (220vac) prototype boards: acedemo acetxrx (315mhz) acetxrxeu (433mhz)

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